Manufacturing a Very Large Scale Integrated Circuit (VLSI) includes hundreds of technological processes. A subtle change in the manufacturing processes may cause a physical defect on a chip, and as a result, the chip cannot work normally.
To ensure quality of a chip at delivery, testing is an essential part in a semiconductor realization process. The testing is actually a process in which a test excitation signal is loaded to an input pin of a semiconductor product that needs to be tested, then a circuit response is tested in an output pin of the semiconductor product, and the circuit response is compared with an expected response to determine whether a circuit is faulty.
Design for testability Design For Testabilility (DFT) becomes an important part in circuit and chip design. Various hardware logics used to improve chip testability are inserted into an original design of a chip, so that the chip becomes easily tested. A scan-based design is a most commonly used method in the design for testability. The scan-based design refers to replacement of ordinary flip-flops (flip-flops) in a circuit with scan flip-flops that have a scan capability and are connected to form a scan chain. The scan chain divides an inner sequential circuit into small combinational circuits, and a test vector is generated by using an Automatic Test Pattern Generator (ATPG) tool. The test vector is input to the inside of the chip by using the scan chain, and a corresponding result generated after the test vector is input is serially output through a specific pin of the chip, to achieve an objective of controlling and observing values of the flip-flops.
However, no system clock exists in a token (token) based asynchronous circuit, and therefore, the circuit cannot be tested in a scan manner.